1. Field of the Invention
The present invention relates generally to an isolation technique for III-nitride devices, and relates more particularly to a device and method for an electro-chemical etch to produce device isolation in III-nitride semiconductor devices.
2. Description of Related Art
III-nitride semiconductors are presently known that exhibit a large dielectric breakdown field of greater than 2.2 MV/cm. III-nitride heterojunction structures are also capable of carrying extremely high currents, which makes devices fabricated in the III-nitride material system excellent for power applications.
Development of devices based on III-nitride materials has generally been aimed at high power-high frequency applications such as emitters for cell phone base stations. The devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction field effect transistors (HFETs), high electron mobility transistors (HEMTs) or modulation doped field effect transistors (MODFETs). These types of devices are typically able to withstand high voltages such as in the range of 100 Volts, while operating at high frequencies, typically in the range of 2-100 GHz. These types of devices may be modified for a number of types of applications, but typically operate through the use of piezoelectric polarization fields to generate a two dimensional electron gas (2 DEG) that allows transport of very high current densities with very low resistive losses. The 2 DEG is formed at an interface of AlGaN and GaN materials in these conventional III-nitride HEMT devices. Due to the nature of the AlGaN/GaN interface, and the formation of the 2 DEG at the interface, devices that are formed in the III-nitride materials system tend to be nominally on, or depletion mode devices. The high electron mobility of the 2 DEG at the interface of the AlGaN/GaN layers permits the III-nitride device, such as a HEMT device, to conduct without the application of a gate potential.
One of the advantages attained with power semiconductor devices for manufacturing purposes is the ability to produce compact structures on a single wafer or on a single die. A number of III-nitride devices can be formed on a given wafer or die to speed production and increase efficiency. When the devices are formed on a wafer or die, they must be isolated from each other to provide proper independent operation. Accordingly, it would be desirable to produce a number of III-nitride power devices on a single wafer or die with some type of insulation or isolation between the devices.
A drawback of III-nitride devices that permit high current densities with low resistive losses is the limited thickness that can be achieved in the strained AlGaN/GaN system. The difference in the lattice structures of these types of materials produces a strain that can result in dislocation of films grown to produce the different layers. This results in high levels of leakage through a barrier layer such as an insulator, for example, and makes device isolation problematic.
One solution to provide isolation is to add insulation barriers around the device to produce the desired isolation and typical layers used for this purpose are silicon oxide, silicon nitride, sapphire, or other insulators, disposed between devices. However, these processes and structures are difficult to implement and are not commercially feasible.
Materials in the gallium nitride material system may include gallium nitride (GaN) and its alloys such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN) and indium aluminum gallium nitride (InAlGaN). These materials are semiconductor compounds that have a relatively wide direct bandgap that permits highly energetic electronic transitions to occur. Gallium nitride materials have been formed on a number of different substrates including silicon carbide (SiC), sapphire and silicon. Silicon substrates are readily available and relatively inexpensive, and silicon processing technology has been well developed.
Another solution to attain isolation in a III-nitride semiconductor device is through the use of a dielectric. For example, in silicon semiconductors, native oxides are available, such as silicon dioxide, that can serve as a suitable dielectric. However, no equivalent material to the native oxides in silicon is available for suitable dielectrics in the III-nitride material system. Dielectric materials that would otherwise be suitable in silicon semiconductors, for example, do not transfer well to III-nitride devices. For example, if silicon dioxide or silicon nitride were to be used for a dielectric in a III-nitride device, these conventional dielectrics may rupture or otherwise fail. Typically, the large dielectric breakdown field produced in the III-nitride material system causes large electric fields in the III-nitride semiconductor devices that are greater than can be withstood with conventional dielectric materials.
High voltage isolation of devices on a substrate is die is known in which different portions of the semiconductor structure are built to have a voltage well, where the device is constructed in the well and, voltage isolated to a particular voltage level. These isolation wells may be formed with a number of barrier structures to prevent leakage from one potential well to another, but such structures are often complicated and expensive to manufacture.
One way to obtain device isolation in conventional semiconductors is to apply a plasma etch process to the semiconductor material surrounding the devices on the substrate or semiconductor die. However, the plasma etch process induces surface damage and roughness in the semiconductor material, which may nevertheless be acceptable for a number of low power, conventional semiconductor devices. However, surface damage and roughness in the semiconductor material is particularly problematic for high power electronic devices where problems develop with surface breakdown and leakage currents between device structures.
Accordingly, it would be desirable to device an isolation technique for devices on a substrate or a semiconductor die that is simple and inexpensive to implement.
It is also desirable to obtain device isolation without a number of additional steps or the use of additional materials.
Furthermore, it would be desirable to provide a technique for device isolation that produces little or no damage to the semiconductor devices or underlying material.